Semiconductor device including a crystal semiconductor layer, its fabrication and its operation

ABSTRACT

In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of application Ser. No. 12/710,378,filed Feb. 23, 2010, which is a Divisional of application Ser. No.11/561,151, filed Nov. 17, 2006, now U.S. Pat. No. 7,696,032, issuedApr. 13, 2010, which claims priority from Korean Patent Application No.2005-0110986, filed Nov. 18, 2005, the disclosure of which is herebyincorporated herein by reference in its entirety as if set forth fullyherein.

BACKGROUND OF INVENTION

1. Technical Field

The present invention relates to a semiconductor device, a fabricatingmethod thereof, and an operating method thereof, and more particularly,to a semiconductor device having a crystalline semiconductor layer, afabricating method thereof, and an operating method thereof.

2. Discussion of the Related Art

With a highly integrated semiconductor device, channel lengths oftransistors and distances, such as between transistors, are small. Andas integration increases, those sizes and distances become smaller.Also, one will find with recent trends that concentrations of impuritiesin semiconductor substrates have increased, and thus, source/drainjunction capacitances of transistors and leakage currents haveincreased. Consequently, the trends result in a deterioration of manyother characteristics of semiconductor devices, such as high speed, lowpower consumption, and the like, though these properties continue to bein increasing demand.

A silicon-on-insulator (SOI) substrate is gaining attention to solvethese problems. Particularly, the SOI is less susceptible to a latch upphenomenon caused by an inner feed-back phenomenon that occurs in a CMOSstructure with high integration density.

The SOI substrate has a single crystal silicon layer formed on a buriedinsulating layer unlike a bulk silicon substrate, and an element such asa transistor is formed on the single crystal silicon layer. Generally,fabrication of the SOI substrate may be divided into two methods. Afirst method is a separation by implanted oxygen (SIMOX) method, inwhich oxygen atoms are implanted into a silicon substrate so that theoxygen atoms penetrate deep into the substrate by a predetermined depth,and an annealing process is performed to form a buried insulating layer.A second method is to form an insulating layer on a substrate and attachsubstrates to each other, and perform an etch-back process on thesubstrates.

A main drawback, however, of the first method is that its processes arecomplicated and inconvenient because a LOCOS process or an STI processmust be performed to form an isolation layer after oxygen ions areimplanted into a silicon substrate, and a thermal treatment process isperformed. Furthermore, serious defects may be generated inside thesemiconductor substrate on which elements will be formed. In the secondmethod, however, since two substrates having an insulating layer formedthereon are attached at a high temperature, and one side of thesubstrates is polished, it is required to perform a thermal treatmentprocess at a high temperature, and voids may be generated at thejunction portion of the substrates.

Recently, as one of the efforts to solve these problems, a method offabricating an SOI substrate is disclosed in U.S. Pat. No. 6,602,758 B2in the title of “Formation of Silicon On Insulator Devices as Add-OnModules for System On a Chip Processing” to Kizilyalli, et al. Accordingto Kizilyalli, et al., an insulating layer is formed on a semiconductorsubstrate, and the insulating layer is patterned, thereby forming anopening exposing the semiconductor substrate. An amorphous silicon layeris formed on the patterned insulating layer to contact the exposedsemiconductor substrate, and an eximer laser is applied to crystallizethe amorphous silicon layer. As a result, a silicon layer havingsubstantially the same single crystal structure as that of thesemiconductor substrate is formed.

However, a continuous effort is required to fabricate an improvedsemiconductor device using a crystalline semiconductor layer formed onthe semiconductor substrate as well as to form the SOI substrate.

SUMMARY

Therefore, some embodiments of the present invention are directed toproviding a semiconductor device and a method of its fabrication capableof forming a semiconductor layer having the substantially same crystalstructure as that of a semiconductor substrate on the semiconductorsubstrate, and interposing various barrier layers between thesemiconductor substrate and the semiconductor layer.

Another embodiment of the present invention is to provide a method ofoperating a semiconductor device having the semiconductor substrate, thesemiconductor layer, and the barrier layer interposed between thesemiconductor substrate and the semiconductor layer.

In accordance with an exemplary embodiment, the present inventionprovides a method of fabricating a semiconductor device having acrystalline semiconductor layer. The method comprises preparing asemiconductor substrate and forming a preliminary active pattern on thesemiconductor substrate. The preliminary active pattern comprises abarrier pattern and a non-single crystal semiconductor pattern, whichmay be alternately stacked at least one time. A sacrificial non-singlecrystal semiconductor layer is formed to cover the preliminary activepattern and the semiconductor substrate. By crystallizing thesacrificial non-single crystal semiconductor layer and the non-singlecrystal semiconductor pattern, using the semiconductor substrate as aseed layer, the sacrificial non-single crystal semiconductor layer andthe non-single crystal semiconductor pattern are changed to asacrificial crystalline semiconductor layer and a crystallinesemiconductor pattern respectively. The crystalline semiconductorpattern and the barrier pattern constitute an active pattern. Thesacrificial crystalline semiconductor layer is preferably removed.

The semiconductor substrate may be a single crystal semiconductorsubstrate.

Forming the preliminary active pattern may comprise sequentially forminga barrier layer and a non-single crystal semiconductor layer on thesemiconductor substrate, and patterning the non-single crystalsemiconductor layer and the barrier layer.

The preliminary active pattern may be formed to further comprise asemiconductor pattern below the barrier pattern. In this case, formingof the preliminary active pattern may comprise sequentially forming abarrier layer and a non-single crystal semiconductor layer on thesemiconductor substrate, patterning the non-single crystal semiconductorlayer and the barrier layer to expose a predetermined portion of thesemiconductor substrate, and etching the exposed semiconductor substrateby a predetermined depth.

After removing the sacrificial crystalline semiconductor layer, themethod may further comprise forming a gate pattern crossing the activepattern. The gate pattern may be formed to comprise a gate insulatinglayer and a gate electrode, which are sequentially stacked.

The insulating pattern may be formed thinner than the gate insulatinglayer.

Before forming the gate pattern, the method may further comprise formingan isolation layer covering the semiconductor substrate around theactive pattern.

Source/drain may be formed inside the active pattern at both sides ofthe gate pattern.

The barrier pattern may be formed to comprise a metal pattern.

The sacrificial crystalline semiconductor layer may have an etchselectivity with respect to the crystalline semiconductor pattern.

When the crystalline semiconductor pattern comprises a silicon layer,the sacrificial crystalline semiconductor layer may be formed of asilicon germanium layer.

In another aspect of the present invention, the present inventionprovides a semiconductor device having a crystalline semiconductorlayer. The semiconductor device comprises a semiconductor substrate, andan active pattern disposed on the semiconductor substrate. The activepattern comprises a barrier pattern and a crystalline semiconductorpattern, which are alternately stacked at least one time, thecrystalline semiconductor pattern having substantially the same crystalstructure as that of the semiconductor substrate.

The semiconductor substrate may be a single crystal semiconductorsubstrate.

The active pattern may further comprise a semiconductor pattern disposedbetween the barrier pattern and the semiconductor substrate. Thesemiconductor pattern may be relatively protruded from the semiconductorsubstrate.

Further, a gate pattern crossing the active pattern may be formed, andsource/drain may be formed inside the active pattern at both sides ofthe gate pattern. The gate pattern may comprise a gate insulating layerand a gate electrode.

In another aspect of the present invention, the present inventionprovides a method of operating a one-transistor memory device. Themethod comprises preparing a One-transistor memory device comprising asemiconductor substrate, an active pattern including a barrier patternand a crystalline semiconductor pattern having substantially the samecrystal structure as that of the semiconductor substrate sequentiallystacked on the semiconductor substrate, a gate insulating layer coveringthe active pattern, a gate electrode disposed on the gate insulatinglayer and crossing the active pattern, and a source and a drain formedinside the active pattern at both sides of the gate electrode. A writevoltage is applied between the semiconductor substrate and the gateelectrode, thereby implanting carriers from the semiconductor substrateinto the crystalline semiconductor pattern.

The method may further comprise applying a read voltage between thesource and the drain, thereby reading out data stored inside theone-transistor memory cell.

The barrier pattern may be a tunnel insulating layer.

The barrier pattern may be thinner than that of the gate insulatinglayer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail preferred embodiments thereof with reference to theattached drawings in which:

FIG. 1 is a plan view illustrating a semiconductor device according toan embodiment of the present invention;

FIGS. 2 through 7 are cross-sectional views taken along line I-I′ ofFIG. 1 illustrating a method of fabricating a semiconductor deviceaccording to embodiments of the present invention;

FIG. 8 is a cross-sectional view illustrating a method of fabricating asemiconductor device according to another embodiment of the presentinvention;

FIGS. 9 through 12 are cross-sectional views taken along line I-I′ ofFIG. 1 illustrating a method of fabricating a semiconductor deviceaccording to yet another embodiments of the present invention;

FIG. 13 is a cross-sectional view taken along line II-II′ of FIG. 1illustrating a method of fabricating a semiconductor device according tostill other embodiments of the present invention; and

FIGS. 14 and 15 are cross-sectional views taken along line II-II′ ofFIG. 1 illustrating a method of driving a memory cell of one transistoraccording to still other embodiments of the present invention.

DETAILED DESCRIPTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thicknesses of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout thespecification.

FIG. 1 is a plan view illustrating a semiconductor device according toan embodiment of the present invention, and FIGS. 2 through 7 arecross-sectional views taken along line I-I′ of FIG. 1 illustrating amethod of fabricating a semiconductor device according to someembodiments of the present invention.

Referring to FIGS. 1 and 2, a semiconductor substrate 100 is prepared.The semiconductor substrate 100 may have a single crystalline structure.The semiconductor substrate 100 may be, for example, a siliconsubstrate, a germanium substrate, a silicon germanium substrate, or asilicon carbide substrate. A barrier layer 105 and a non-single crystalsemiconductor layer 110 are sequentially formed on the overall surfaceof the semiconductor substrate 100. The non-single crystal semiconductorlayer 110 may be formed of a silicon layer, a germanium layer, a silicongermanium layer, or a silicon carbide layer.

Herein, the “non-single crystal semiconductor layer” may be in anamorphous state. The “non-single crystal semiconductor layer” cancontain some proportion of microcrystalline or polycrystalline material.

The barrier layer 105 may be an insulating layer. The insulating layermay include, for example, a silicon oxide layer, a silicon nitridelayer, an oxide/nitride/oxide (ONO) layer, or a high-k dielectric layer.The barrier layer 105 and the non-single crystal semiconductor layer 110may be stacked alternately at least one time. The barrier layer 105 mayhave different functions depending on its kind and formation thickness.

For example, when the barrier layer 105 comprises silicon oxide, thebarrier layer 105 may function as a buried insulating layer of a siliconon insulator (SOI) substrate. On the other hand, the barrier layer 105may also function as a tunnel insulating layer. In this case, thebarrier layer 105 may be formed relatively thin. According to someembodiments of the present invention, since the thickness of the barrierlayer 105 is easy to control, the thickness of the barrier layer 105 maybe formed less than that of a buried insulating layer of a conventionalSOI substrate. For example, the barrier layer 105 may be formed with athickness of about 100 Å or less.

When the barrier layer 105 comprises an ONO layer or a high-k dielectriclayer in other embodiments, the barrier layer 105 may function as atunnel insulating layer. In the meantime, when the barrier layer 105comprises silicon nitride in other embodiments, the barrier layer 105may function as a charge storage layer.

Referring to FIGS. 1 and 3, the non-single crystal semiconductor layer110 and the barrier layer 105 are patterned, thereby forming apreliminary active pattern 115 a including a barrier pattern 105 a and anon-single crystal semiconductor pattern 110 a, which are sequentiallystacked. From a plan view, the preliminary active pattern 115 a may beformed with a line shape or an island shape.

A sacrificial non-single crystal semiconductor layer 120 is formed tocover the preliminary active pattern 115 a and the semiconductorsubstrate 100. The sacrificial non-single crystal semiconductor layer120 may comprise a material having an etch selectivity with respect tothe semiconductor substrate 100 and the non-single crystal semiconductorpattern 110 a. For example, when the semiconductor substrate 100 and thenon-single crystal semiconductor pattern 110 a comprise silicon, thesacrificial non-single crystal semiconductor layer 120 may comprisesilicon germanium.

Referring to FIGS. 1 and 4, the sacrificial non-single crystalsemiconductor layer 120 and the non-single crystal semiconductor pattern110 a are crystallized using the semiconductor substrate 100 as a seedlayer. The sacrificial non-single crystal semiconductor layer 120 andthe non-single crystal semiconductor pattern 110 a can be crystallizedusing, for example, a solid phase epitaxial (SPE) technology. Thecrystallization process may include a thermal treatment indicated as anarrow 123 (FIG. 4) using a laser beam. During the thermal treatment 123,the non-single crystal semiconductor pattern 110 a and the sacrificialnon-single crystal semiconductor layer 120 are changed to a crystallinesemiconductor pattern 110 c and a sacrificial crystalline semiconductorlayer 120 c respectively. The sacrificial non-single crystalsemiconductor layer 120 is crystallized to have substantially the samecrystal structure as that of the material layer in contact with thesacrificial non-single crystal semiconductor layer 120 during thethermal treatment 123. That is, when the semiconductor substrate 100 hasa single crystal structure, the sacrificial non-single crystalsemiconductor layer 120 is crystallized to have substantially the samecrystal structure as that of the semiconductor substrate 100, namely, asingle crystal structure. Similarly, since the non-single crystalsemiconductor pattern 110 a is covered with the sacrificial crystallinesemiconductor layer 120 c, the non-single crystal semiconductor pattern110 a is changed to the crystalline semiconductor pattern 110 c havingsubstantially the same crystal structure as that of the sacrificialcrystalline semiconductor layer 120 c during the thermal treatment 123.For example, when the sacrificial crystalline semiconductor layer 120 chas a single crystal structure, the non-single crystal semiconductorpattern 110 a is also crystallized to have a single crystal structure.As a result, the non-single crystal semiconductor pattern 110 a iscrystallized to have substantially the same crystal structure as that ofthe semiconductor substrate 100 through the sacrificial non-singlecrystal semiconductor layer 120. The crystalline semiconductor pattern110 c and the barrier pattern 105 a disposed therebelow constitute anactive pattern 115 c. That is, the preliminary active pattern 115 a ischanged to the active pattern 115 c after the thermal treatment 123.

Referring to FIGS. 1 and 5, the sacrificial crystalline semiconductorlayer 120 c is removed. The sacrificial crystalline semiconductor layer120 c may be selectively removed, using an isotropic etch process.Alternatively, the sacrificial crystalline semiconductor layer 120 c maybe removed employing an etch process using an etch selectivity. Forexample, when the semiconductor substrate 100 and the crystallinesemiconductor pattern 110 c comprise silicon, and the sacrificialcrystalline semiconductor layer 120 c comprises silicon germanium, thesacrificial crystalline semiconductor layer 120 c can be selectivelyremoved using an etchant selectively removing the silicon germanium.

Referring to FIGS. 1 and 6, a planarized isolation layer 131 is formedon the semiconductor substrate 100 having the active pattern 115 c. Theformation of the isolation layer 131 may include forming an isolationinsulating layer 130, for example, a silicon oxide layer on the overallsurface of the semiconductor substrate 100 having the active pattern 115c, and planarizing the isolation insulating layer 130 to expose theactive pattern 115 c. Before the isolation insulating layer 130 isformed, a liner insulating layer 125 such as a silicon nitride layer maybe formed. When the liner insulating layer 125 is formed before theisolation insulating layer 130 is formed, the method may further includeprocesses of planarizing the isolation insulating layer 130 andselectively removing the liner insulating layer 125 remained on theactive pattern 115 c.

In other embodiments, the isolation layer 131 may be formed so that itsupper surface is on substantially the same plane as an upper surface ofthe active pattern 115 c, or may be formed to have a lower level orhigher level than the level of the upper surface of the active pattern115 c. When the upper surface of the isolation layer 131 is lower thanthe upper surface of the active pattern 115 c, sidewalls of the activepattern 115 c as well as the upper surface thereof are partiallyexposed, thereby forming a fin-shaped active pattern 115 c.

Referring to FIGS. 1 and 7, a gate pattern 150 is formed to cross theactive pattern 115 c. The gate pattern 150 may be formed to include agate insulating layer 133 formed on the active pattern 115 c, a gateelectrode 135 crossing the active pattern 115 c, and a gate cappingpattern 145 disposed on the gate electrode 135. A source 160 a and adrain 160 b are formed inside the active pattern 115 c on both sides ofthe gate pattern 150. Specifically, the source 160 a and the drain 160 bmay be formed inside the crystalline semiconductor pattern 110 c.

FIG. 8 is a cross-sectional view illustrating a method of fabricating asemiconductor device according to another embodiment of the presentinvention.

Referring to FIG. 8, an active pattern 115 c′ including a barrierpattern 105 a and a crystalline semiconductor pattern 110 c′ is formedon a semiconductor substrate 100 by the same or similar method asdescribed with reference to FIGS. 2 through 5. The barrier pattern 105 amay be a metal pattern unlike the embodiment illustrated in FIG. 7. Themetal pattern may be a metal pattern not influenced by a thermaltreatment 123 to form the crystalline semiconductor pattern 110 c′. Thatis, when the thermal treatment 123 is performed using a laser and at atemperature of about 600.degree. C., the metal pattern is preferably ametal pattern having a melting point higher than about 600.degree. C.The metal pattern may function as a word line or a bit line.

An insulating layer is formed on the overall surface of thesemiconductor substrate 100 having the active pattern 115 c′, and theinsulating layer is planarized to expose the active pattern 115 c′,thereby forming an insulating interlayer 132. Then, n-type impurity ionsare implanted into a lower portion of the crystalline semiconductorpattern 110 c′, using the insulating interlayer 132 as an ionimplantation mask, thereby forming an n-type semiconductor pattern 110 ncontacting the barrier pattern 105 a. Then, p-type impurity ions areimplanted into an upper portion of the crystalline semiconductor pattern110 c′, thereby forming a p-type semiconductor pattern 110 p on then-type semiconductor pattern 110 n. As a result, the crystallinesemiconductor pattern 110 c′ may function as a diode.

Then, a data storage element 175 may be formed to be in contact with thep-type semiconductor pattern 110 p. The data storage element 175 mayinclude a phase change material pattern or a magnetic tunnel junctionstructure. In this case, the barrier pattern 105 a may function as aword line.

FIGS. 9 through 12 are cross-sectional views taken along line I-I′ ofFIG. 1 illustrating a method of fabricating a semiconductor deviceaccording to yet another embodiment of the present invention, and FIG.13 is a cross-sectional view taken along line II-II′ of FIG. 1.

Referring to FIGS. 1 and 9, a barrier layer 105 and a non-single crystalsemiconductor layer 110 are sequentially formed on the overall surfaceof the semiconductor substrate 100, using the same method as describedin reference to FIG. 2. The barrier layer 105 may be an insulatinglayer.

The non-single crystal semiconductor layer 110 and the barrier layer 105are patterned, thereby forming a barrier pattern 105 a and a non-singlecrystal semiconductor pattern 110 a, which are sequentially stacked,while exposing a predetermined portion of the semiconductor substrate100. The exposed semiconductor substrate 100 is etched by apredetermined depth, thereby forming a semiconductor pattern 100 a. Thesemiconductor pattern 100 a, the barrier pattern 105 a, and thenon-single crystal semiconductor pattern 110 a, which are sequentiallystacked, constitute a preliminary active pattern 115 a″. In the presentembodiment unlike the embodiment illustrated in FIG. 3, the preliminaryactive pattern 115 a″ may be formed to further include the semiconductorpattern 100 a compared to the preliminary active pattern 115 a of FIG.3. Then, a sacrificial non-single crystal semiconductor layer 120 isformed to cover the preliminary active pattern 115 a″ and thesemiconductor substrate 100.

Referring to FIGS. 1, 10, and 11, the semiconductor substrate 100 havingthe sacrificial non-single crystal semiconductor layer 120 is thermallytreated 123. The non-single crystal semiconductor pattern 110 a and thesacrificial non-single crystal semiconductor layer 120 are changed to acrystalline semiconductor pattern 110 c and a sacrificial crystallinesemiconductor layer 120 c respectively during the thermal treatment 123.In the embodiments as described above, when the semiconductor substrate100 has a single crystal structure, the sacrificial non-single crystalsemiconductor layer 120 and the non-single crystal semiconductor pattern110 a are crystallized to have substantially the same crystal structureas that of the semiconductor substrate 100, that is, a single crystalstructure. After the thermal treatment 123, the preliminary activepattern 115 a″ is changed to an active pattern 115 c″. Then, thesacrificial crystalline semiconductor layer 120 c is selectivelyremoved. An isolation layer 131″ may be formed on the semiconductorsubstrate 100 around the active pattern 115 c″. The isolation layer 131″may be formed to expose sidewalls of the semiconductor pattern 100 a,the barrier pattern 105 a, and the crystalline semiconductor pattern 110c.

Referring to FIGS. 1, 12, and 13, a gate insulating layer 133 is formedon a sidewall of the semiconductor pattern 100a, a sidewall of thecrystalline semiconductor pattern 110 c, and an upper surface of thecrystalline semiconductor pattern 110 c. The gate insulating layer 133may be formed of a thermal oxide layer. A gate electrode 135 and a gatecapping pattern 145 are sequentially formed on the gate insulating layer133 to cross the active pattern 115 c″. The gate insulating layer 133,the gate electrode 135, and the gate capping pattern 145 constitute agate pattern 150.

First and second sources 160 a and 160 a″, and first and second drains160 b and 160 b″ are formed inside the active pattern 115 c″ on bothsides of the gate pattern 150. The first source 160 a and the firstdrain 160 b may be formed inside the crystalline semiconductor pattern110 c. The second source 160 a″ and the second drain 160 b″ may beformed inside the semiconductor pattern 100 a. In this case, the firstsource 160 a and the first drain 160 b may be formed to have aconductivity type identical to that of the second source 160 a″ and thesecond drain 160 b″ or different conductivity type from that of thesecond source 160 a″ and the second drain 160 b″.

Hereinafter, a structure of a semiconductor device according toembodiments of the present invention will be explained in reference toFIGS. 1, 7, 8, 12 and 13.

Referring to FIGS. 1 and 7, a semiconductor substrate 100 is provided.The semiconductor substrate 100 may have a single crystal structure. Thesemiconductor substrate 100 may be a silicon substrate, a germaniumsubstrate, a silicon germanium substrate, or a silicon carbidesubstrate. An active pattern 115 c is disposed on the semiconductorsubstrate 100. The active pattern 115 c includes a barrier pattern 105 aand a crystalline semiconductor pattern 110 c, which are sequentiallystacked. The crystalline semiconductor pattern 110 c has substantiallythe same crystal structure as that of the semiconductor substrate 100.The barrier pattern 105 a may be an insulating pattern. The insulatingpattern may be a silicon oxide pattern, a silicon nitride pattern, anONO pattern, or a high-k dielectric pattern. The barrier pattern 105 amay have a thickness of about 100 Å or less. The barrier pattern 105 aand the crystalline semiconductor pattern 110 c are stacked one on topof the other, and, further, may be alternately stacked repetitively.

An isolation layer 131 may be formed on the semiconductor substrate 100around the active pattern 115 c. The isolation layer 131 may include anisolation insulating layer 130 and a liner insulating layer 125surrounding the isolation insulating layer 130. An upper surface of theisolation layer 131 may be disposed at substantially the same level asthat of an upper surface of the active pattern 115 c, or may be disposedat the level higher or lower than that thereof.

A gate pattern 150 is disposed to cross the active pattern. The gatepattern 150 may include a gate insulating layer 133, a gate electrode135, and a gate capping pattern 145, which are sequentially stacked. Thegate insulating layer 133 may be a thermal oxide layer.

When the upper surface of the isolation layer 131 is disposed lower thanthe upper surface of the active pattern 115 c, the active pattern 115 cmay be formed to have a fin-shaped structure. That is, a sidewall of theactive pattern 115 c may overlap the gate pattern 150. On the contrary,when the upper surface of the isolation layer 131 is disposed higherthan the upper surface of the active pattern 115 c, the gate electrode135 may be disposed to be self-aligned. A source 160 a and a drain 160 bmay be disposed inside the active pattern 115 c at both sides of thegate pattern. Specifically, the source 160 a and the drain 160 b may bedisposed inside the crystalline semiconductor pattern 110 c.

Referring to FIG. 8, a semiconductor device according to anotherembodiment of the present invention will be explained. First, asemiconductor substrate 100 is provided. An active pattern 115 c′ isdisposed on the semiconductor substrate 100. The active pattern 115 c′includes a barrier pattern 105 a and a crystalline semiconductor pattern110 c′, which are sequentially stacked. The barrier pattern 105 a mayinclude a metal pattern. The crystalline semiconductor pattern 110 c′may include an n-type semiconductor pattern 110 n having n-typeimpurities, and a p-type semiconductor pattern 110 p disposed on then-type semiconductor pattern 110 n and having p-type impurities. In thiscase, the crystalline semiconductor pattern 110 c′ may function as adiode. An insulating interlayer 132 is disposed on the semiconductorsubstrate 100 having the crystalline semiconductor pattern 110 c′.

A data storage element 175 electrically connected to the active pattern115 c′ is disposed on the insulating interlayer 132. The data storageelement 175 may include a phase change material pattern or a magnetictunnel junction structure.

Referring to FIGS. 1, 12 and 13, a semiconductor device according toanother embodiment of the present invention will be explained. An activepattern 115 c″ is disposed on the semiconductor substrate 100. Theactive pattern 115 c″ includes a semiconductor pattern 100 a, a barrierpattern 105 a, and a crystalline semiconductor pattern 110 c, which aresequentially stacked. In the present embodiment unlike the embodimentillustrated in FIG. 7, the semiconductor pattern 100 a is disposed belowthe barrier pattern 105. The semiconductor pattern 100 a may havesubstantially the same crystal structure as that of the semiconductorsubstrate 100. An isolation layer 131″ may be disposed on thesemiconductor substrate 100 around the active pattern 115 c″.

A gate pattern 150 is disposed to cross the active pattern 115 c″. Thegate pattern 150 may include a gate insulating layer 133, a gateelectrode 135, and a gate capping pattern 145, which are sequentiallystacked. The gate pattern 150 may be disposed to overlap a sidewall ofthe active pattern 115 c″ as well as an upper surface thereof.

First and second sources 160 a and 160 a″, and first and second drains160 b and 160 b″ may be provided inside the active pattern 115 c″ onboth sides of the gate pattern 150. The first source 160 a and the firstdrain 160 b may be formed inside the crystalline semiconductor pattern110 c. The second source 160 a″ and the second drain 160 b″ may bedisposed inside the semiconductor pattern 100 a. In this case, the firstsource 160 a and the first drain 160 b may have conductivity typeidentical to that of the second source 160 a″ and the second drain 160b″ or different conductivity type from that thereof. As a result, aplurality of transistors may be provided. Particularly, when the firstsource 160 a and the first drain 160 b have different conductivity typefrom that of the second source 160 a″ and the second drain 160 b″, thesemiconductor device may function as a CMOS device.

FIGS. 14 and 15 are cross-sectional views taken along line II-II′ ofFIG. 1 illustrating a one-transistor memory device fabricated accordingto an embodiment of the present invention, and a method of driving thesame.

Referring to FIGS. 1, 14 and 15, an active pattern 115 c is disposed ona semiconductor substrate 100. The active pattern 115 c may include abarrier pattern 105 a and a crystalline semiconductor pattern 110 c,which are sequentially stacked. The barrier pattern 105 a may be atunnel insulating layer. A gate insulating layer 133 is disposed on theactive pattern 115 c. The barrier pattern 105 a may be thinner than thatof the gate insulating layer 133 such that the barrier pattern 105 a canfunction as a tunnel insulating layer. The barrier pattern 105 may havea thickness of about 100 Å or less. A gate electrode 135 is disposed onthe gate insulating layer 133. A source 160 a and a drain 160 b aredisposed inside the crystalline semiconductor pattern 110 c on bothsides of the gate electrode 135.

A transistor illustrated in FIGS. 1, 14 and 15 may be used as aone-transistor memory, e.g., DRAM cell without a cell capacitor. Amethod of driving the one-transistor DRAM device with the one-transistorDRAM cell will be explained.

Data corresponding to logic ‘0’ is assumed as an initial state, and awrite voltage Vw is applied between the gate electrode 135 and thesemiconductor substrate 100 to write data corresponding to logic ‘1’ tothe DRAM cell so that carriers are moved from the semiconductorsubstrate 100 to the crystalline semiconductor pattern 110 c bytunneling. That is, by grounding the semiconductor substrate 100 andapplying a positive write voltage Vw to the gate electrode 135,electrons are tunneled from the semiconductor substrate 100 to thecrystalline semiconductor pattern 110 c. As a result, a channel regionformed inside the crystalline semiconductor pattern 110 c has differentpotentials in a logic state ‘0’ and a logic state ‘1’. At this time, thesource 160 a and the drain 160 b may be grounded or may be floated.

To read data of the DRAM cell, a read voltage VR is applied between thesource 160 a and the drain 160 b, to read out data stored in theone-transistor memory cell. The read voltage VR may be in a range ofabout 0.5 V to 2.0 V.

According to some embodiments of the present invention, the barrierpattern 105 a may be formed thinner than a buried insulating layeremployed to a conventional SOI substrate. That is, since the barrierpattern 105 a is formed relatively thin, it may function as a tunnelinsulating layer. As a result, desired data can be stored by tunnelingcarriers when driving a one-transistor memory cell.

According to some embodiments of the present invention as describedabove, an active semiconductor layer having substantially the samecrystal structure as that of a semiconductor substrate may be formed onthe semiconductor substrate. Furthermore, various applicable devices canbe fabricated by appropriately selecting a kind and a thickness of abarrier layer interposed between the semiconductor substrate and theactive semiconductor layer.

While this general inventive concept has been described in terms ofseveral preferred embodiments, there are alternations, permutations, andequivalents, which fall within the scope of this invention. It shouldalso be noted that there are many alternative ways of implementing themethods and apparatuses of the present general inventive concept. It istherefore intended that the following appended claims be interpreted asincluding all such alternations, permutations, and equivalents asfalling within the true spirit and scope of the present disclosure.

1. A semiconductor device comprising, a semiconductor substrate havingfirst source/drain regions; an active pattern on the semiconductorsubstrate, the active pattern comprising a barrier pattern and a singlecrystalline semiconductor pattern on the barrier pattern; and a gatepattern on the single crystalline semiconductor pattern.
 2. Thesemiconductor device according to claim 1, wherein the singlecrystalline semiconductor pattern has second source/drain regions. 3.The semiconductor device according to claim 2, wherein the secondsource/drain regions are vertically aligned and disposed at both sidesof the gate pattern.
 4. The semiconductor device according to claim 1,wherein the first source/drain regions are vertically aligned anddisposed at both sides of the gate pattern.
 5. The semiconductor deviceaccording to claim 1, wherein the gate pattern comprises a gateinsulating layer and a gate electrode on the gate insulating layer. 6.The semiconductor device to claim 1, wherein the gate pattern comprisesa gate insulating layer and a gate electrode on the gate insulatinglayer.
 7. The semiconductor device according to claim 1, wherein thesemiconductor substrate and the single crystalline semiconductor patternhaving the same single crystalline structures.